High-speed comparators are used in modern high-speed electronics, for instance in analog-to-digital converters (ADC). Two types of comparators commonly used in high speed applications are dynamic comparators and static comparators. Dynamic comparators can offer an advantage of no static power consumption and no hysteresis, due to a reset phase after the comparison. However, dynamic comparators can also have disadvantages such as high kick-back noise and high sensitivity to process, supply voltage, and temperature (PVT) variations. Meanwhile, static comparators may be realized with a comparably small number of transistors, provide inductive peaking possibilities, generally do not suffer from kick-back noise issues and are comparably robust against PVT variations. Static comparators can be employed in extremely high-speed applications, for instance in flash ADCs. However, static comparators have static power consumption.
FIG. 1 shows a static comparator 1 with schematically indicated master and slave latches 2, 3. The master latch 2 comprises, as shown in the enlargement, an amplifier circuit 4 in the form of a differential pair, and an associated latch circuit 5. The amplifier circuit 4 and the latch circuit 5 may, as shown, be alternatingly coupled to a current sink 6 (or alternatively to ground through a high resistance) in accordance with complementary clock signals CLK, CLK˜. The slave unit 3 has a corresponding configuration. The static comparator 1 may as shown further comprise a programmable offset compensation current source 7 with a sign controlled by complementary static inputs SIGN, SIGN˜ that determine the sign of the offset correction to be applied.